The invention relates generally to semiconductor devices and a method of fabricating the same and, more particularly, to semiconductor devices and a method of fabricating the same, in which gate patterns are formed.
In general, in a flash memory semiconductor device, gate patterns are formed by patterning a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, and a gate electrode.
FIG. 1 is a sectional view of a semiconductor device for forming gate patterns of the device in the prior art.
Referring to FIG. 1, a tunnel insulating layer 11, a conductive layer for a floating gate 12, a dielectric layer 13, a conductive layer for a control gate 14, a gate electrode layer 15, and a hard mask layer 16 are sequentially stacked over a semiconductor substrate 10. The hard mask layer 16 is patterned and the gate electrode layer 15 is then patterned by an etch process using the patterned hard mask layer.
Generally, in the case in which a tungsten silicide (WSix) layer is used as a gate electrode layer in semiconductor devices of 50 nm or less, resistance (Rs) of word lines is increased due to a high resistivity of the tungsten silicide (WSix) layer itself, resulting in low program and read speeds. To solve the problem, the thickness of the tungsten silicide (WSix) layer must be increased. However, this method makes the process of patterning the word lines more difficult and may cause voids within isolation layers that electrically isolate the word lines. Accordingly, research has been done on a method of forming a gate electrode layer using a tungsten (W) layer having lower resistivity than the tungsten silicide (WSix) layer.
However, the tungsten layer is easily oxidized by a thermal process and easily corroded or oxidized and dissolved by a cleaning agent in a cleaning process. Accordingly, this method also greatly limits subsequent processes.